Towards Low-Power On-chip Auditory Processing

Towards Low-Power On-chip Auditory Processing

Machine perception is a difficult problem both from a practical or implementation point of view as well as from a theoretical or algorithmic point of view. Machine perception systems based on biological perception systems show great promise in many areas but they often have processing requirements and/or data flow requirements that are difficult to implement, especially in small or low-power sy...

Towards low-power yet high-performance networks-on-chip

A network-on-chip (NoC), the de-facto communication backbone in manycore processors, consumes a significant portion of total chip power, competing against the computation cores for the limited power and thermal budget. On the other hand, overall system performance of manycore chips increasingly relies on on-chip latency and bandwidth as core counts scale. This thesis aims to design low-power ye...

Low Power Networks-on-Chip

Network on-Chip (NoC) is an interconnect fabric to connect sub-system blocks on a chip. The NoC should provide high bandwidth and low latency, should consume low energy, and should be compact. However, all these requirements are at odds and require tradeoffs at all levels. In this chapter, we discuss issues and challenges for future NoCs with demands for high bandwidth and low energy. Next, we ...

‏‎design of an analog ram (aram)chip with 10-bit resolution and low-power for signal processing in 0/5m cmos process‎‏

برای پردازش سیگنال آنالوگ در شبکه های عصبی ، معمولا نیاز به یک واحد حافظه آنالوگ احساس میشود که بدون احتیاج به ‏‎a/d‎‏ و‏‎d/a‎‏ بتواند بطور قابل انعطاف و مطمئن اطلاعات آنالوگ را در خود ذخیره کند. این واحد حافظه باید دارای دقت کافی ، سرعت بالا ، توان تلفاتی کم و سایز کوچک باشد و همچنین اطلاعات را برای زمان کافی در خود نگهدارد. برای پیاده سازی سیستمی که همه این قابلیتها را در خود داشته باشد، کوشش...

Low - Power Low - Jitter On - Chip Clock Generation